The high cost associated with manufacturing integrated circuits dictates that defective devices be diagnosed and dealt with as early as possible in the manufacturing line. For this reason, it is highly advantageous to test integrated circuits at 1 the wafer level before further processing and packaging. Circuits are tested on wafers by first clamping the wafer to a chuck and then placing highly sophisticated probes in contact with the circuit devices. These probes must utilize pressure in order to make adequate electrical contact to test the devices, and therefore may apply forces up to 100 psi onto the wafer. Once probe contact is made, the circuits are tested for both functionality and power integrity. Large scale integrated circuits may have to be tested at power levels in excess of 100 watts, which consequently generates a tremendous amount of heat build up in the chips.
The chucks which clamp wafers during the aforementioned testing process must provide structural support for the wafer in order to withstand the pressure from the test probe, hold the wafer in place, achieve and maintain specified chuck temperatures, and provide heat sinking capability to maintain the wafer within the thermal specifications.
A popular way of cooling ICs for testing in the prior art was to dice the wafer up into single chips, mount the chips onto substrates and then test the chip while utilizing a variety of methods to conduct heat away from the substrate to which the chip was mounted. Applications for this type of approach can be found in U.S. Pat. Nos. 4,920,574 (Yammamoto, et al.), 4,897,762 (Daikoku, et al.) and 4,942,497 (Mine, et al.). The techniques disclosed in these patents are unfavorable, though, because they require processing beyond the wafer stage of the manufacturing process before testing can begin.
Another technique utilized to cool integrated circuits during manufacturing test is to spray a high volume of liquid against the back side of the chip during the testing. Typical systems which utilize this technique are disclosed in U.S. Pat. Nos. 4,750,086 (Mittal); and 4,967,832 (Porter). These systems have also proven to be unfavorable, though, because of the high rate of water which is required for the cooling and also because probe pressures must be kept at an absolute minimum due to the lack of structural support for the wafer.
In another testing environment, vacuum and electrostatic clamping are also utilized to hold wafers to chucks, thereby creating a dry interface between the wafer and chuck. The chuck itself is then cooled in some manner to provide heat transfer from a chip through the chuck. The dry film interface in these systems represents a high thermal resistivity which severely limits the amount of testing which can be performed to the wafer due to the fact that high power chips produce high localized heat build-up on the wafer itself. In some of these dry interface systems, a dry gas such as helium is injected between the wafer and the chuck to help provide a better heat conductor. It is difficult, however, to reduce the thermal resistance of these dry interface chucks below 1.1.degree.C./watt thermal resistivities.
A clamping and cooling system for high power integrated circuit test at the wafer level which overcomes the above mentioned deficiencies is, therefore, highly desirable.